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Digital design · FPGA

Flappy Bird on FPGA

Building a real-time game entirely in hardware

No game engine, no software loop driving the graphics — the entire game lives in SystemVerilog on the Urbana FPGA board. A MicroBlaze soft processor handles USB input while custom RTL modules render video, run the physics, and detect collisions in real time.

Role
RTL design — team of 2
Course
ECE 385, UIUC
Timeframe
Fall 2023
Language
SystemVerilog
Read the report (PDF) ↗
Flappy Bird rendered live from the FPGA board
// Flappy Bird rendered in real time from FPGA hardware.

01 Overview

The player flaps with the space bar and threads gaps between scrolling green pillars, scoring one point per pillar. On top of the base game we added live difficulty control (keys 1/2 change scroll speed), selectable background schemes (A/S), and an invincible mode (I) where the bird destroys pillars instead of dying. Rendering targets a standard 640×480 display over VGA/HDMI.

02 Hardware architecture

The top module stitches together a MicroBlaze soft processor and an AXI interconnect (handling USB-HID keyboard input, UART, interrupts and DMA) with custom display RTL. The game itself is split into focused, independently testable modules:

  • VGA controller — generates hsync/vsync and the active draw region from the pixel clock.
  • Ball — the bird's vertical dynamics: gravity, jump impulse on keypress, and screen-boundary handling.
  • Pillar — continuously scrolls obstacles right-to-left and recycles them at the edge.
  • Color mapper — pulls sprites from ROMs initialized by COE files to color each pixel per game element.
  • State machine — a 50 MHz FSM over START → GAME → INVINCIBLE → END, gating collision detection by state.
  • Collision — compares the bird's edges against four pillars (top, bottom, front) plus the ground.

03 Build progression

I brought the game up incrementally: first the space-bar jump and a gravity model, then sprite mapping, collision checking, start/game-over screens, scoring, background scrolling, a procedural column-height algorithm, a wing-flap animation, and finally the user-controllable settings — each a separate, verifiable RTL increment.

04 Synthesis results

8,089
LUTs (3,108 FF)
55.5 MHz
Max frequency
0.51 W
Total power

Final design statistics from Vivado: 8,089 LUTs, 3,108 flip-flops, 21 DSP slices, 73.5 BRAM tiles, 55.54 MHz, and 0.508 W total power — a compact, fully self-contained hardware game.